Units: 1.5, Hours: 3-3
Boolean algebra, canonical expressions, logic gates and their physical realization. Fan-in and fan-out, timing, rise and fall times, delay. Combinational circuits minimization (Karnaugh map, Quine-McCluskey, Tools-Expresso, others). Standard circuits - adders, multiplexers, demultiplexers, etc. Memory elements, flip-flops. State transition diagrams, Mealy-Moore finite state machines. State assignment and machine realization, counters. Introduction to Verilog and its use to design combinational and sequential circuits. Advanced topics to include design with PLDs, PLAs, FPGAs.
Note: Credit will be granted for only one of 241, 290.
Prerequisites: Second-year standing.
Undergraduate course in Computer Engineering offered by the Computer Engineering in the Faculty of Engineering.