CENG 441

Design of Digital and VLSI Systems

Units: 1.5

Hours: 3-1.5

Advanced combinational and sequential logic design. Optimization of finite state machines; timing methodologies and synchronization issues. Hardware description languages (HDL): structural and behavioural descriptions, simulation and testbenches, coding styles, design with HDL and FPGA implementation. Design for test: testing concepts, scan-based design and built-in self-test (BIST). Design for high speed: timing analysis, pipelining and retiming. Design for low power: sources of power dissipation, design transformations.


  • Credit will be granted for only one of CENG 441, CENG 440, CENG 465.


  • CENG 241 or CENG 290; and
  • minimum fourth-year standing in the Faculty of Engineering.

Undergraduate course in Computer Engineering offered by the Department of Electrical and Computer Engineering in the Faculty of Engineering.

Fall 2017 Spring 2018 Summer 2018

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